engineering the solar age - Suppliers for Photovoltaics

The manufacture of modules from crystalline silicon cells requires a number of process steps and different production technologies. While the manufacture of thin-film modules is a continuous process in which physical deposition techniques (sputtering, vapor deposition) dominate.

To permit the production of wafers, the solar grade silicon is first crystallized into blocks or ingots. Often boron is added to the silicon at this early processing stage, causing p-doping of the crystal structure.

Crystal growing, i.e. the synthetic production of monocrystals, is required for the production of monocrystalline ingots. Two methods have been proved in practice:

• In the Czochralski process, the silicon crystal is pulled from a crucible containing molten polycrystalline silicon. The starting point for crystallization is a monocrystalline silicon seed crystal that is immersed in the melt and onto which the silicon atoms deposit themselves in a regular pattern. The seed’s rod is slowly pulled upwards and rotated simultaneously so that a cylindrical monocrystal of around 30 cm diameter is extracted. This ingot can be several meters long.
• The zone melting process allows crystallization with simultaneous purification. A polycrystalline silicon rod is induction-heated to melting point at one end, i.e. a powerful current is induced in the inner core of the rod that heats the material to its melting point. The narrow melt zone travels along the length of the rod so that the material behind the molten zone resolidifies. As the melting point of the impurities differs from that of the silicon, the phase change from molten to solidified separates the impurities from the silicon. The impurities accumulate in the melt and are transported to the end of the rod as the molten zone travels through the rod so that they can be cut off after the end has solidified.

A multiple stage process is required to transform the around 180 µm thick wafers into solar cells. First, the saw damage is removed by wet chemical etching. It is possible to roughen up the surface of the wafer at the same time in this step, to increase the absorption of sunlight. The wafers are cleaned in a wet chemical process after etching and then dried.

The silicon structure is then dosed with phosphorus (n-doping). The wafers are exposed to a gas containing phosphorus in a diffusion furnace at around 900 °C in oxygen, which leads to the formation of an oxide with phosphorus on the surface. Phosphorus atoms diffuse from this layer into the silicon structure so that the front side of the wafer is formed into an emitter across its entire surface. The depth to which the phosphorus atoms penetrate depends in particular on the temperature and the duration of diffusion.

Then the phosphorus glass (phosphorus silicate) created on the surface is removed by a wet chemical treatment.

To increase sunlight absorption and to improve the electrical properties of the surfaces and the base material, an anti-reflection coating (silicon nitride) is applied to the front side of the wafer. Plasma enhanced chemical vapor deposition (PECVD) has proved itself the most effective method.

Extremely narrow conductors (contact fingers) are then screen-printed onto the front side of the wafer using a silver paste and two or three wider tracks (busbars) perpendicular to these through which the charge carriers can be removed. Busbars are printed on the rear side with a silver/aluminum paste. The wafer is dried in a special furnace after each print process. Finally, the contacts are fired to create an electrical connection with the silicon.

The grid and the busbars inevitably cover a proportion of the cell surface, which reduces light absorption. For this reason, rear-side contacts are gaining in importance.

Eight to twelve solar cells are joined to form a string, connected with one another by soldered contact ribbons and thereby connected electrically in series. The strings are then soldered to one another. A number of strings (generally six) form a module which consequently consists of 48 to 96 cells, as a rule.

The soldered solar cells are embedded in plastic film – either of ethyl vinyl acetate (EVA) or of polyvinyl butyral (PVB) – and encased between a glass plate on the front side and a weather-resistant plastic film (usually Tedlar) on the rear side. The rear side may also consist of a glass plate. Only highly transparent, anti-reflection coated or structured glass is used for the front sheet of glass.

The complete sandwich is then baked in a laminator in a vacuum and at a temperature of around 140 °C. The important point here is to heat the entire module surface up uniformly and rapidly. The crystalline module is finally sealed at the edges with tape, an aluminum frame with silicon sealant and a junction box is fitted on the rear side.

CIS and CIGS: The production of thin-film modules from copper indium gallium selenide or copper indium gallium sulfite (CIGS) and from copper indium selenide or copper indium sulfite (CIS) begins by coating the glass substrate with molybdenum to create a rear-side contact. This is done by sputtering. The p-type CIS or CIGS absorber coating is produced either by vapor deposition onto the heated substrate or in a multistage process in which first copper and indium are deposited onto the unheated substrate. Selenization or sulfurization follows in a subsequent step known as baking.

A CdS buffer film and a ZnO film create the p-n junction. At the same time, the zinc oxide forms the transparent front contact (TCO film). The CdS buffer film is generally deposited in a chemical bath and the front contact is created by cathode evaporation (sputtering).

The challenge is to achieve two improvements at once: First, to increase productivity by reducing material costs, increasing plant throughput (process speed) and improving plant availability (automation).

Secondly, to increase the conversion efficiency by minimizing optical losses (light traps), improved exploitation of the solar spectrum and finally by reducing the electrical losses.

Only if the rate of learning in fundamental research is sustained over the long term will it be possible to push the ratio of minimum cost per electrical output towards the target value of less than 1/W.

In a scenario for the period from 2010 to 2020, the ITRPV calculates an annual industrial growth rate of 35 percent and a learning rate of 20 percent. This yields a yearly cost reduction of between eight and nine percent, depending on the quantity of modules produced. If we look at this with regard to output, the reduction in costs is even greater (nine to ten percent), as module efficiency is set to increase.

Manufacturing costs and efficiency are the two factors which ensure that module costs fall dramatically. It is foreseeable, however, that manufacturing costs will be the dominating factor over the next decade and beyond.

Some of the systems used to produce Si wafer solar cells originate from microelectronics manufacturing. They have already been adapted for markedly higher throughputs and the line cycle times last only seconds, making them 30 to 200 times faster than the line cycle times for thin-film solar cells which take minutes. However, there is still room to increase throughput and lower costs even further.

One option is to use larger ingots. The roadmap announced that the mass of a monocrystalline ingot will rise from around 150 kg at present to approximately 300 kg over the next ten years. The multicrystalline ingots that today weigh around 400 kg will then weigh more than one metric ton.

Within the same period, it will also be necessary to improve the productivity of tools by increasing the yield and throughput of production lines. This primarily affects the wafer sawing and wafer cleaning production steps where the throughput of each tool could be increased by around 50 percent.

Tool uptime as defined by SEMI standard E10 is another important factor that can be used to optimize production lines. The goal is to attain an uptime of over 96 percent. This is already achieved today in the chemical process steps of cell production, but will not be reached in metallization and classification until 2015.

In order to increase the throughput of the entire production line, front-end (chemical and thermal) and back-end (metallization and classification) processes must be adapted to one another (synchronized).

Currently, the front end is rushing way ahead of the back end. The front end must process 3,600 wafers per hour as a minimum, but at the back end this total is just 3,000 wafers. In ten years, it is to be expected that front-end output will reach at least 7,200 wafers per hour. To close the gap, significantly faster metallization technologies will be employed to enable the back end to match this total.

In order to achieve the target cost reductions, production machinery should have a smaller footprint (45 percent less by 2020) and require fewer staff (minus 60 percent by 2020) while yielding a higher throughput. Moreover, the processes of interconnecting and encapsulating cells must be made quicker. Amongst other things, this will require encapsulation materials that permit shorter processing times.

A surge in throughput rates is to be expected in around 2015 if new interconnection technologies and rear contacting are introduced into mass production.

Several measures are needed to improve the efficiency of cells. These include both reducing recombination losses and increasing emitter sheet resistance. By 2015, it will be possible to make the width of front contacts distinctly smaller by using new technology in the metallization process. At around the same time, silver printing will be superseded by copper plating, resulting in further cost reductions.

The key objective is to extract as much output as possible from the interconnected cells. A good yardstick for this is the module-to-cell power ratio. This value is currently 97.5 percent for multicrystalline, and 96 percent for monocrystalline silicon. By introducing anti-reflective glass into module production, it will be possible to improve these values by around 1.5 percentage points from 2013. Two years later, new interconnection and encapsulation technologies will increase them by a further percentage point, meaning that in principle a ratio of 100 percent will be achieved.

Over the next few years, the efficiency of multicrystalline cells is set to rise dramatically, allowing them to keep pace with developments in monocrystalline cells. It is anticipated that the 20-percent limit will be reached in 2020. This can be attributed in part to the fact that rear-contact cells will increasingly gain acceptance. The proportion of these cells on the market will soar from 2014 onward and will reach 40 percent by 2020.

Furthermore, statistical process control (SPC) is necessary to continually improve all manufacturing steps. This detects all the errors in individual process stages and assesses their impact on the subsequent process steps. Productivity can thus be increased even further by performing these checks.

The range of interesting possibilities offered by laser technology assists in developing new cell concepts. The most important advantages are:

• alternatives to photolithography that can be implemented on an industrial scale
• high speed (ten thousand holes can be made in wafers in seconds)
• contact-free wafer processing
• minimal heat input

Processes where laser beams are applied to only a small proportion of the surface stand a particularly good chance of gaining wide acceptance in future.

New beam sources with ever higher repetition rates and capabilities are being launched onto the laser market. In addition, new possibilities for beam shaping and beam guidance are continually being created. This will enable the structuring of large solar cell surface areas to be performed cheaply in industrial-scale production.